1. Field of the Invention
The present invention relates generally to methods for forming damascene structures within microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced reliability, damascene structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. Such comparatively low dielectric constant dielectric materials generally have dielectric constants. For comparison purposes, microelectronic dielectric layers formed within microelectronic fabrications from conventional silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically have comparatively high dielectric constants. Similarly, such patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are typically formed within microelectronic fabrications while employing damascene methods, including in particular dual damascene methods.
Microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as such microelectronic dielectric layers formed of dielectric materials having comparatively low dielectric constants provide microelectronic fabrications which may theoretically operate at higher microelectronic fabrication speeds, with attenuated patterned microelectronic conductor layer parasitic capacitance and attenuated patterned microelectronic conductor layer cross-talk.
Similarly, damascene methods are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials insofar as damascene methods are comparatively simple fabrication methods which may often be employed to fabricate microelectronic structures which are not otherwise practicably accessible in the art of microelectronic fabrication.
While damascene methods are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications, damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications. In that regard, while damascene methods are generally successful for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications, such damascene methods are often difficult to employ for forming, with high reliability, patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications.
It is thus desirable in the art of microelectronic fabrication to provide damascene methods which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with enhanced reliability.
It is towards the foregoing object that the present invention is directed.
Various damascene methods have been disclosed in the art of microelectronic fabrication for forming within microelectronic fabrications damascene structures with desirable properties in the art of microelectronic fabrication.
Included among the damascene methods, but not limited among the damascene methods, are damascene methods disclosed within Yao et al., in U.S. Pat. Nos. 6,054,379 and 6,072,227 (a pair of methods and apparatus for forming within a microelectronic fabrication a multiplicity of dielectric layers formed of comparatively low dielectric constant dielectric materials in turn formed incident to oxidation of an organosilane, preferably methylsilane, silicon and carbon source material, wherein the dielectric layers may be employed as etch stop layers, as well as other types of layers, within microelectronic fabrication structures within microelectronic fabrications including but not limited to dual damascene microelectronic fabrication structures within microelectronic fabrications).
Desirable in the art of microelectronic fabrication are additional damascene methods and materials which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with enhanced reliability.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
A second object of the present invention is to provide a damascene method in accord with the first object of the present invention, wherein the patterned microelectronic conductor layer is formed with enhanced reliability.
A third object of the present invention is to provide a damascene method in accord with the first object of the present invention and the second object of the present invention, wherein the damascene method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate. There is then formed upon the substrate a barrier layer, where the barrier layer comprises: (1) a carbon doped silicon nitride layer formed upon the substrate; and (2) a carbon doped silicon oxide layer formed upon the carbon doped silicon nitride layer.
Within the method of the present invention, and when the barrier layer is formed as a first etch stop/liner layer upon a substrate having formed therein a contact region which is accessed employing a damascene structure within the microelectronic fabrication, the method of the present invention provides for: (1) attenuated oxidation of the contact region when forming the first etch stop/liner layer; and (2) attenuated residue formation when forming, photo exposing and developing a photoresist layer upon the first etch stop/barrier layer, thus in turn providing enhanced reliability of a patterned conductor layer formed within the damascene structure within which is formed the barrier layer of the present invention.
There is provided by the present invention a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material, wherein the patterned microelectronic conductor layer is formed with enhanced reliability.
The present invention realizes the foregoing object by forming upon a substrate employed within a microelectronic fabrication a barrier layer, where the barrier layer comprises: (1) a carbon doped silicon nitride layer formed upon the substrate; and (2) a carbon doped silicon oxide layer formed upon the carbon doped silicon nitride layer.
Within the method of the present invention, and when the barrier layer is formed as a first etch stop/liner layer upon a substrate having formed therein a contact region which is accessed employing a damascene structure within the microelectronic fabrication, the method of the present invention provides for: (1) attenuated oxidation of the contact region when forming the first etch stop/liner layer; and (2) attenuated residue formation when forming, photo exposing and developing a photoresist layer upon the first etch stop/barrier layer, thus in turn providing enhanced reliability of a patterned conductor layer formed within the damascene structure within which is formed the barrier layer of the present invention.
The method in accord with the present invention is readily commercially implemented.
As will be illustrated in greater detail within the context of the Description of the Preferred Embodiment, as set forth below, the method of the present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of specific process limitations and specific materials limitations to provide the method of the present invention. Since it is thus at least in part a series of specific process limitations and specific materials limitations which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.